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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
Mixed-Mode Operation
The device can support a combination of synchronous READ and asynchronous WRITE
operations when the BCR is configured for synchronous operation. The asynchronous
WRITE operation requires that the clock (CLK) be held static LOW or HIGH during the
entire sequence. The ADV# signal can be used to latch the target address, or it can
remain LOW during the entire WRITE operation. CE# must return HIGH when transi-
tioning between mixed-mode operations. Note that the t CKA period is the same as a
READ or WRITE cycle. This time is required to ensure adequate refresh. Mixed-mode
operation facilitates a seamless interface to legacy burst mode Flash memory control-
lers. See Figure 41 on page 51.
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, system-
level WAIT signal (see Figure 10). The shared WAIT signal is used by the processor to
coordinate transactions with multiple memories on the synchronous bus.
Figure 10:
Wired-OR WAIT Configuration
External
READY
C ellularRAM
WAIT
Pull-Up/
Pull-Down
Resistor
WAIT
Other
WAIT
Other
Pro c essor
Devi c e
Devi c e
Once a READ or WRITE operation has been initiated, WAIT goes active to indicate that
the CellularRAM device requires additional time before data can be transferred. For
READ operations, WAIT will remain active until valid data is output from the device. For
WRITE operations, WAIT will indicate to the memory controller when data will be
accepted into the CellularRAM device. When WAIT transitions to an inactive state, the
data burst will progress on successive clock edges.
During a Burst cycle, CE# must remain asserted until the first data is valid. Bringing CE#
HIGH during this initial latency may cause data corruption.
The WAIT output also performs an arbitration role when a READ or WRITE operation is
launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted
for additional clock cycles until the refresh has completed (see Figures 11 and 12 on
page 17). When the refresh operation has completed, the READ or WRITE operation will
continue normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary.
The WAIT assertion allows time for the new row to be accessed and permits any pending
refresh operations to be performed.
LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data transfers. During READ
operations, the enabled byte(s) are driven onto the DQ. The DQ associated with a
disabled byte are put into a High-Z state during a READ operation. During WRITE opera-
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2005 Micron Technology, Inc. All rights reserved.
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